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Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADM1176
VCC 1
10 GATE
SENSE 2
ON 3
GND 4
TIMER 5
ADM1176
TOP VIEW
(Not to Scale)
9
8
7
6
A1
A0
SDA
SCL
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
Mnemonic
VCC
SENSE
ON
GND
TIMER
SCL
SDA
A0
A1
GATE
Description
Positive Supply Input Pin. The operating supply voltage range is from 3.15 V to 16.5 V. An undervoltage
lockout (UVLO) circuit resets the ADM1176 when a low supply voltage is detected.
Current Sense Input Pin. A sense resistor between the VCC pin and the SENSE pin sets the analog current
limit. The hot swap operation of the ADM1176 controls the external FET gate to maintain the (V CC ? V SENSE )
voltage at or below 100 mV.
Undervoltage Input Pin. Active high pin. An internal undervoltage comparator has a trip threshold of 1.3 V,
and the output of this comparator is used as an enable for the hot swap operation. With an external resistor
divider from VCC to GND, the ON pin can be used to enable the hot swap operation for a specific voltage on
VCC, providing an undervoltage function.
Chip Ground Pin.
Timer Pin. An external capacitor, C TIMER , sets a 270 ms/μF initial timing cycle delay and a 21.7 ms/μF fault delay.
The GATE pin turns off when the TIMER pin is pulled beyond the upper threshold. An overvoltage detection
with an external Zener can be used to force this pin high.
I 2 C Clock Pin. Open-drain input requires an external resistive pull-up.
I 2 C Data I/O Pin. Open-drain input/output. Requires an external resistive pull-up.
I 2 C Address Pin. This pin can be tied low, tied high, left floating, or tied low through a resistor. Sixteen I 2 C
address options are available, depending on the external configuration of the A0 pin and the A1 pin.
I 2 C Address Pin. This pin can be tied low, tied high, left floating, or tied low through a resistor. Sixteen I 2 C
address options are available, depending on the external configuration of the A0 pin and the A1 pin.
GATE Output Pin. This pin is the high-side gate drive of an external N-channel FET. This pin is driven by the
FET drive controller, which utilizes a charge pump to provide a 12.5 μA pull-up current to charge the FET
GATE pin. The FET drive controller regulates to a maximum load current (100 mV through the sense resistor)
by modulating the GATE pin.
Rev. C | Page 7 of 24
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